The University of Sydney

报告摘要：

A key virtue of spin qubits is their tiny, submicrometre footprint, which enables billions of qubits to fit on a single silicon wafer. However, with each qubit requiring a handful of gate electrodes for control, management of this extreme interconnect density is challenging. Monolithic integration of qubits with CMOS-based control circuits might address this challenge, although the effect of heat and crosstalk on the qubits is likely to pose a substantial risk to this approach. An alternative architecture [1] uses heterogeneous ‘chiplet’-style packaging in which the control circuits and qubits are proximal, but positioned on separate dies and wired-up using dense, lithographically defined interconnects at millikelvin temperatures. Here, we report the realisation of a cryo-CMOS control architecture (based on 28-nm fully depleted silicon-on-insulator) and benchmark its performance using silicon MOS-style electron spin qubits [2]. The fidelity of single- and two-qubit gate operations acts to probe the effect of heat and noise arising from the cryo-CMOS control circuits. These results suggest that heterogeneous integration is a viable means of scaling-up the control interface of spin-based quantum processors.

[1] Pauka, S. J. et al. A cryogenic CMOS chip for generating control signals for multiple qubits. Nat. Electron. 4:64–70 (2021).

[2] Veldhorst, M. et al. A two-qubit logic gate in silicon. Nature 526:410–414 (2015).

邀请人：Hiroki Ikegami

联系人：袁晓旭（yuanxiaoxu@iphy.ac.cn）

地点：中国科学院物理研究所-怀柔园区-X1南楼204会议室